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DS1280 3-wire to bytewide converter chip DS1280 021998 1/11 features ? adapts jedec bytewide memory to a 3-wire serial port ? supports 512k bytes of memory ? 68-pin version provides arbitration mechanisms for dual port operation ? cmos circuitry design for battery backup and battery operate applications ? cyclic redundancy check monitors serial data transmission for error ? available in 44- or 80-pin quad flat pack for high den- sity requirements ordering information DS1280fp-xx -80 80-pin flat pack -44 44-pin flat pack pin description rst reset for serial port dq data input/output for serial port clk clock input for serial port dqe serial port active output ceb system bus enable oeb system bus read enable web system bus write enable a0b-a18b system address bus d0b-d7b system data bus cer ram chip enable wer ram write enable oer ram output enable a0r-a18r ram address bus d0r-d7r ram data bus gnd ground v cc +5 volts pin assignment 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc dq d7b d7r d6b d6r d5b d5r d4b d4r d3b d3r d2b d2r d1b d1r d0b d0r a18b nc nc nc nc nc a2b a3r a3b a4r a4b a5r a5b a6r a6b a7r a7b a8r a8b a9r a9b a10r a10b a11r nc nc nc nc nc nc a2r a1b a1r a0b a0r rst clk gnd vcc dqe ceb cer web wer oeb oer a11b a12b a12r a13r a13b a14r a14b gnd vcc a15r a15b a16r a16b a17r a17b a18r 1 2 3 4 5 6 7 8 9 10 11 DS1280fp-80 80-pin flat pack see mech. drawings section 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 DS1280fp-44 44-pin flat pack see mech. drawings section nc a18r a17r a16r a15r vcc gnd a14r a13r a12r nc oer wer cer dqoe vcc gnd clk rst a0r a1r a2r nc dq d7r d6r d5r d4r d3r d2r d1r d0r nc nc a3r a4r a5r a6r a7r a8r a9r a10r a11r nc description the DS1280 adds a 3-wire serial port to a bytewide stat- ic ram yet maintains the existing bytewide port. memory capacity of up to 512k bytes can be addressed directly. arbitration between the serial and bytewide port is accomplished by handshaking or using predict- able idle time as an access window. the serial port re- quires a 6-byte protocol to set up memory transfers. cy- clic redundancy check circuitry is included to monitor serial data transmission for error.
DS1280 021998 2/11 pin description rst the 3-wire serial port selection signal input. when rst is low, all communications to the serial port are inhibited. when high, data is clocked into or out of the serial port. clk the clock input signal is used to input or extract data from the 3-wire serial port. a clock cycle is defined as a falling edge followed by a rising edge. data is driv- en out onto the 3-wire bus after a falling edge during read cycles and latched into the port on the rising edge during write cycles. dq the dq signal is the bidirectional data signal for the 3-wire serial port. byte 0 bit 0 is the first bit input/out- put . dqe the dqe output signal is active (high level) whenever the 3-wire serial port is driving the dq line. therefore, this pin will be high whenever data is being read. otherwise it will be low and the dq line will be an input. this signal can be used as a means of tri-stating the dq driver on the other end. cer chip enable output to ram. this signal is as- serted active (low) during ram read or write cycles. this signal is either derived from the system bus chip enable (ceb ) or from a 56-bit protocol provided by the 3-wire serial port and associated timing circuits. wer write enable output to ram. this signal is as- serted active (low) during ram write cycles. this signal is either derived from the system bus write enable (web ) or from a 56-bit protocol provided by the 3-wire serial port and associated timing circuits. oer output enable to ram. this signal is asserted active (low) during ram read cycles. this signal is ei- ther derived from the system bus read enable (oeb ) or from a 56-bit protocol provided by the 3-wire serial port and associated timing circuits. a0r-a18r addresses supplied to ram. these sig- nals allow access to up to 512k bytes of ram controlled by the DS1280. the addresses are either derived from the system address bus (a0b-a18b) or from the proto- col and internal binary counter provided by the 3-wire serial port and associated timing circuits. d0rd7r data bus supplied to ram. these eight signals comprise the bidirectional data bus between ex- ternal bytewide ram and the DS1280. this data bus is either derived from the system data bus (d0b-d7b) or from the protocol and data stream provided by the 3-wire serial port and associated timing circuits. ceb system bus chip enable to the DS1280. this sig- nal is used to generate the ram chip enable for transfer of data to and from the parallel system bus to ram (68-pin package only). oeb system bus output enable (read) for transfer of data from ram to the parallel system bus (68-pin pack- age only). web system bus write enable to the DS1280. this signal is used to generate the ram write enable for transfer of data from the parallel system bus to the ram (68-pin package only). a0b-a18b system bus addresses to the DS1280. these signals are used to specify the address location for data transfer to and from ram (68-pin package only). d0b-d7b system data bus to and from the DS1280. this bidirectional bus is used to carry data to and from the parallel system bus and ram (68-pin package only). vcc +5volt power from the DS1280 (2 pins). gnd ground for the DS1280 (2 pins). operation figure 1 illustrates the main elements of the DS1280. as shown, the DS1280 has two major sections: a 3-wire to bytewide converter and a serial/parallel multiplexer. the source of the serial/parallel multiplexer is either a 3wire serial port or a bytewide system bus. arbitration of the serial/parallel multiplexer is controlled by signals from the 3-wire to bytewide converter. the 3-wire serial port, therefore, has priority in accessing the ram and the methods used to avoid collisions are primarily di- rected by the 3-wire to bytewide converter.
DS1280 021998 3/11 DS1280 block diagram figure 1 dqe serial port buffers system port control buffers system parallel port address buffers 3-wire to bytewide converter serial/parallel address mux with arbitration byte detect i/o buffers with arbitration byte and direction control logic serial/system control mux a01-a18r ram address bus d0r-d7r ram data bus d0b-d7b system data bus a0b-a18b system address bus DS1280q-68 DS1280q-80 only ceb oeb web rst clk dq cer oer wer system bytewide parallel bus if the rst signal for the 3-wire serial port is low (inac- tive), the bytewide parallel port can access associated ram directly. the bytewide parallel bus addresses (a0b-a18b) and control signals (ceb , oeb and web ) are buffered by the DS1280 and become outputs a0r-a18r, cer , oer , and wer respectively, which are connected directly to ram. the data input/output signals (d0b-d7b) are internally buffered and sent to ram on the data input/output signals d0r-d7r. the buffering is designed to handle bidirectional data trans- fer. data will be written from the bytewide parallel bus to ram when ceb and web inputs are both active (low). the oeb signal is a ``don't careo signal during a write cycle. data is read from ram via the byte wide parallel port when ceb and oeb signals are both low and web is high. 3-wire serial bus if the rst signal for the 3-wire serial port is active (high), the 3-wire to bytewide converter controls the ram through the control/address/data multiplexers. the 3-wire to bytewide converter uses a 56-bit protocol writ- ten serially using rst , dq, and clk to determine the action required and also the starting address location in the ram to be used. data is entered into the 3-wire while rst is high on the low-to-high transition of the clk signal provided the data is stable on the dq line with the proper setup and hold times. the last eight bits of the 56-bit protocol are a cyclic redundancy check byte (crc) that ensures that all bits of the protocol have been received correctly. if the 56 bits of protocol have not been received correctly, further action will be aborted. the crc check byte can catch up to three single bit errors within the 56-bit protocol and can also be used on incoming and outgoing serial data streams to check the integrity of data being read or written. more discussion on crc use and crc generation will follow later in this text.
DS1280 021998 4/11 protocol: 3-wire serial bus the 3-wire serial bus protocol can cause eight different actions to occur as shown in table 1. the organization of the 56-bit protocol is shown in fig- ure 2. as defined, the first byte of the protocol deter- mines whether the action which is to occur involves a read or write. a read function is defined by the binary pattern 11101000. this pattern, therefore, applies to commands 1, 3, 5, and 6 of table 1. a write function is defined by the binary pattern 00010111. this pattern, therefore, applies to commands 2, 4, 7, and 8 of table 1. any other pattern which is entered into the read/write field will cause further action to terminate. additional dif- ferentiation as to which read or write command is deter- mined by the last five bits of the third byte of the protocol called the command field. the control field bits are de- fined in table 2 . a burst read uses a 19-bit address field which consists of the second, third, and bits 0, 1, and 2 of the fourth byte of the protocol to determine the starting address of infor- mation to be read from ram. the byte of data resident in that location is loaded into an 8-bit shift register within the DS1280. the byte of data is then transferred from the shift register to the 3-wire bus by driving the dq line on the falling edge of the next eight clocks with the lsb first. a burst write uses the same 19-bit address field to determine the starting address of information to be writ- ten into ram. data is shifted from the dq line of the 3-wire bus into an 8-bit shift register within the DS1280 on the next eight rising clock edges. after a byte is loaded, the data is written into the ram location immedi- ately after the rising edge of the eighth clock. burst reads and writes will continue on a byte-by-byte basis, automatically incrementing the selected address by one location for each successive byte. protocol commands table 1 1. burst read 2. burst write 3. read protocol select bits 4. write protocol select bits 5. burst read masking portions of the protocol select bits 6. read crc register 7. set the address arbitration byte location 8. poll arbitration byte for status and control termination of a current operation will occur at any time when rst is taken low. if a byte of data has been loaded into the shift register, a write cycle is allowed to finish, so corrupted data is not written into the ram. if a full byte of data has not been loaded into the shift register when rst goes low, no writing occurs. reads can be termi- nated at any point since there is no potential for corrup- tion of data. the read crc command provides a meth- od for checking the integrity of data sent over the 3-wire bus. the crc byte resides in the last byte (byte 6) of the protocol. the 8-bit crc byte not only operates on the protocol bits as they are written in, but also on all data that is written or read from ram. after a burst read or write has finished and rst has gone low, the final value of the crc is stored in the DS1280. if a read crc register command is issued, the stored crc value is driven onto the dq line by the first eight clock cycles after the protocol is received. the crc value generated by the DS1280 should match ex- actly with the value generated in the host system which is transmitting or receiving data on the other end of the 3-wire bus. if it does not, data has been corrupted and a retransmission should occur. it should be noted that the crc for the previous transaction can only be obtained if a read crc command is issued immediately after rst goes low to reset the DS1280, then high to accept a read crc command. if any other sequence is followed, an intermediate crc will be generated and stored whenever rst goes low again, destroying the crc val- ue of interest. generation of the crc byte by the exter- nal unit on the 3-wire bus will be covered later in this data sheet. command field table 2 00110 burst read 10001 burst write 00011 read crc register 10110 set arbitration byte address to 00000 or 7ffff 01001 poll arbitration byte for access to ram 00101 read protocol select bits 01110 write protocol select bits 11xxx burst read masking portions of the select bits
DS1280 021998 5/11 protocol figure 2 msb lsb command field address bits byte 3 msb lsb address bits msb lsb byte 2 byte 4 msb lsb select bits byte 5 msb lsb cyclic redundancy check byte 6 msb lsb byte 1 msb lsb byte 0 select bits address bits read/write function field f a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 a10 a9 a8 ff ff f ff c a18 a17 a16 s7 s6 s5 s4 s3 s2 s1 s0 s15 s14 s13 s12 s11 s10 s9 s8 xxx xxxxx c c c c in any 2-port system there is a potential for access colli- sions. to solve this problem, an arbitration byte is pro- vided so that the serial and parallel ports of the DS1280 can determine the status of the other port. a special byte in ram address space is reserved to allow for handshaking between the two ports. this arbitration byte has a special attribute in that it is simultaneously accessible by both ports. two commands are used by the 3-wire serial port proto- col to manage the arbitration byte. first, since this byte will create a hole in ram address space for the parallel bytewide port, a command is added to move the arbitra- tion byte to either address location ``00000o or address location ``7ffff.o when setting the arbitration byte ad- dress location, the correct read/write field and com- mand field must be entered along with all zeroes or all ones in the address field. it is important to note that the arbitration byte is located in the parallel memory loca- tion assigned by the serial port using the appropriate commands. however, the physical byte of ram is lo- cated within the DS1280. the existence of this physical byte is transparent to the bytewide parallel port and looks like normal ram space with some read/write re- striction. however, the serial port can still address the actual ram location at either 00000 or 7ffff in addi- tion to accessing the arbitration byte. the second command used by the 3-wire serial port provides for polling of the arbitration byte to determine the status of the parallel port. in addition, the arbitration byte can be set to indicate to the parallel port that the se- rial port is taking over the ram. the second command protocol allows the serial port to do a compressed read- write-read operation that causes the arbitration byte to be read by the first eight clocks following the protocol. the next eight clocks cause data to be written into the arbitration byte, and the last eight clock cycles allow for a second read of the data for verification. the 24 cycles occur by entering the 56-bit protocol only once. the pro- tocol pattern entered is a write function in the read/write field (00010111) and the correct command field. select bits three other commands are used to set the select bits in the protocol. once the select bits are set to a binary val- ue they must be matched exactly when protocol is sent or further activity is prevented. the bits allow for 65,536 different binary combinations. therefore, multiple DS1280s can be connected on the same serial bus and only the appropriate device will respond. to write the select bits, a write function in the read/write field is re- quired along with the appropriate command in the com- mand field. to read the select bits, a read cycle in the read/write field is required along with the appropriate command in the command field. the arrangement of reading and writing select bits allows the user to have multiple DS1280s in
DS1280 021998 6/11 use and uniquely identify each. a read can occur suc- cessfully without knowing the select bits but a write can- not occur without matching the current select field. a third command masking specific select bits provides a means for determining the identity of a specific DS1280 when more than one is used. a read in the read/write field and a ``11000o in the command field will execute a mask read that ignores all select bits to determine the presence of one or more DS1280s. with the detection of at least one device, a search can begin by masking all but a single pair of DS1280 select bits. a read in the read/write field and a ``11001o in the command field will unmask the first two lsbs of byte 4 of the select bits (see figure 3). with these two select bits unmasked, only an exact match of four possible combinations of these two select bits will allow access through the 3-wire port to ram. the combinations are 00, 01, 10, and 11. therefore, repeating the unmasking of the first two bits of the select field up to four times will give the binary val- ue of these select bits. having determined the first two select bits, the next two select bits can be unmasked, and the process of match- ing one of four combinations can proceed as before. repetition of unmasking select bit pairs will yield an ex- act match of 65,536 possible DS1280s in no more than 32 attempts. arbitration as mentioned earlier, one byte of ram has been re- served for arbitration between the 3-wire port and the bytewide parallel bus. the location of this byte within the memory map will be at address 00000 or at address 7ffff as determined by the protocol input from the 3-wire serial port. the arbitration byte has special re- strictions and disciplines so that the 3-wire serial bus and the bytewide parallel bus are never in contention for ram access. this byte is shown in figure 4. as defined, the 3-wire serial port can read the whole byte but can only write bits s2-s0. the bytewide paral- lel port can read the whole byte but can only write bits b1-b0. an internal counter controls bits c2-c0 that can- not be written by either port. arbitration is accomplished when the status bits are read and written by the respec- tive ports. if the 3-wire serial port wants to access ram, the arbitration byte should be polled by the serial port until bit b1 equals zero. if b1 equals zero, the 3-wire se- rial port should then write a one into bit s2. after the write of bit s2, the 3-wire serial port should then read the arbitration byte to confirm that b1=0 and s2=1. this op- eration must be executed with the protocol for the com- pressed read/write/read sequence which minimizes overhead. the 3-wire serial port should always abort any attempt to access ram if b1 equals one. when the 3-wire serial port completes any transfer of data to or from ram, bit s2 should be written back to zero so that the bytewide parallel port will know that the 3-wire serial port is not us- ing the ram. the bytewide serial bus can gain access to ram by polling the arbitration byte until s2 bit equals zero. when s2 equals zero, the bytewide parallel port then writes a one into bit b1. a read cycle verifying that s2 equals zero and b1 equals one confirms that the by- tewide parallel port has access to ram. the bytewide parallel port can then read or write ram as required. when the entire transaction is complete, the bytewide parallel port should write the b1 bit to zero, signaling the 3-wire serial port that the ram is not in use. the bits b0, s1, and s0 can be defined by the user to pass additional arbitration information, making possible more elaborate handshaking schemes between the two ports. some typical uses for these bits could be an indi- cation that a port desires access to ram or the amount of ram written. another method of arbitration between the 3-wire serial port and the bytewide parallel bus is the use of the count bits c0-c2. the 3-wire port reads or writes from ram only once every eight clock cycles. this action occurs when the internal byte counter transi- tions from a ``111o state to a ``000o state. the access oc- curs regardless of the arbitration byte status bits. c0-c2 are updated as the internal serial bit counter is increm- ented. the bytewide port can execute reads or writes depending on the status of c0-c2. these bits indicate the number of bits the 3-wire serial port has loaded and, therefore, indicate when a read or write will occur from the 3-wire port. since the 3-wire port always reads or writes at the ends of a byte (c0-c2 = 1) the bytewide parallel bus should never access ram if the count bits read all ones. the bytewide parallel port can determine the minimum time left before the 3-wire serial port will access the memory from the count bits and the minimum clock cycle applied to the 3-wire clock input. essentially the 3-wire serial port is given priority on access to ram and the bytewide parallel port determines when it can access the ram to avoid colliding with the 3-wire serial port.
DS1280 021998 7/11 select bits mask figure 3 lsb msb select bits unmask 2 lsb's unmask 4 lsb's unmask 6 lsb's unmask 8 lsb's unmask 10 lsb's unmask 12 lsb's unmask 14 lsb's mask all byte 5 byte 4 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 command field 1x 0 1 1 1 11 1 1 1 11 1 1 xx 00 0 0 00 0 00 0 0 1 arbitration byte figure 4 c2 s1 s0 msb lsb p1 p0 s2 c1 c0 parallel bus status bits not used serial port status bits count bit not used not used count bit count bit crc generation the logic involved in crc generation is shown in figure 5. it is comprised of an 8-bit shift register, four exclusive or gates, and two sets of transmission gates. the transmission gates serve to divert data from dqin to the crc generator while each byte is being assembled and, at the same time, output data to the output (dq out). when input select crc (sdcrc) is driven to an active level (high), data is output at dqout from the crc generator using the clock input (ck) in the same manner as described earlier for operation of the 3-wire serial bus. the reset signal (rsb) must be high while the crc gen- erator is being used, as an inactive state will disable the 8-bit shift register. this signal is the same as the reset described for the 3-wire serial bus. a crc generator for serial port communications can be constructed as de- scribed above to satisfy the DS1280 crc require- ments. however, another approach is to generate the crc using software. an example of how this is accom- plished using assembly language follows. this assem- bly language code is written for the ds5000 soft micro- controller. the assembly language procedure do crc given below calculates the cumulative crc of all the bytes passed to it in the accumulator. before it is used to calculate the crc of a data stream, it should be initial- ized by setting the variable crc to zero. each byte of the data is then placed in the accumulator and do crc is called to update the crc. after all the data has been passed to do crc, the variable crc will contain the re- sult.
DS1280 021998 8/11 crc generation logic table 3 do_crc: push acc ; save the accumulator push b ; save the b register push acc ; save bits to be shifted mov b, #8 ; set to shift eight bits crc_loop: xrl a, crc ; calculate dqin xor crcto rrc a ; move it to the last mov a, crc ; get the last crc value jnc zero ; skip if dqin xor crcto = 0 xrl a, #0cch ; update the crc value zero: rrc a ; position the new crc mov crc, a : store the new crc pop acc : get the remaining bits ' rr a ; position next bit in lsb push acc ; save the remaining bits djnz b, crc_loop ; repeat for eight bits pop acc ; clean up the stack pop b ; restore the b register pop acc ; restore the accumulator ret ; return crc generation figure 5 dqin sdcrc ck rsb crct7 crct6 crct5 crct4 crct3 crct2 crct1 crct0 b a b a b a a b dqout b a d c rb q d c rb q d c rb q d c rb q d c rb q d c rb q d c rb q d c rb q c c c c c c c c
DS1280 021998 9/11 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to+125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a =0 c to 70 c) parameter symbol min typ max units notes supply v cc 3.25 5.0 6.5 v 1 logic 1 v ih 2.2 v cc +0.3v v logic 0 v il -0.3 +0.8 v 1 dc electrical characteristics (t a =0 c to 70 c ; v cc =+5v 10%) parameter symbol min typ max units notes input leakage i il -1 +1 m a 9 output leakage i lo 1 m a output current @ 2.4v i oh -1 ma output current @ 0.4v i ol +2 ma supply current i cc1 15 ma 2 supply current i cc2 50 ma 3 ac electrical characteristics (v cc =5v 10%; 0 c to 70 c) parameter symbol min typ max units notes data to clk setup t dc 35 ns 4 data to clk hold t cdh 40 ns 4 data to clk delay t cdd 125 ns 4,5,6 clk low time t cl 500 ns 4 clk high time t ch 500 ns 4 clk frequency f clk dc 1 mhz 4,10 clk rise & fall time t r t f 100 ns rst to clk setup t cc 1 m s 4 clk to rst hold t cch 40 ns 4 rst inactive time t cwh 125 ns 4 rst to d/q high z t cdz 50 ns 4,6 serial port active t di 25 ns 4,6 serial port inactive t di 25 ns 4,6 parallel port propagation t pd 12 20 ns 4,6,8
DS1280 021998 10/11 capacitance parameter symbol min typ max units notes input capacitance c in 10 pf output capacitance c out 15 pf notes: 1. all voltages are referenced to ground. 2. i cc1 is measured with all outputs open and both the 3-wire serial port or the bytewide parallel port inactive. 3. i cc2 is measured with all outputs open. 4. measured at v ih = 2.0 v or v il = 0.8v and 10ns maximum rise and fall time. 5. measured at v oh = 2.4 v and v ol = 0.4v. 6. measured with a load capacitance of 50 pf. 7. the 3-wire serial port will correctly read and write any static ram with an effective access time of 200ns. 8. propagation delay is the same for data going either way on the bytewide parallel bus. 9. pins a0b through a18b, rst , dq, ceb have pulldown resistors which will leak approximately 50 m a. 10. arbitration byte must be accessed at a maximum clock frequency of 500 khz with a symmetrical waveform. timing diagram: write data transfer 3-wire serial port (7) reset clock data input/ output t cwh t cch t f t r t ch t cl t cc t dc t cdh o 1
DS1280 021998 11/11 timing diagram: read data transfer 3-wire serial port (7) reset dqe clock t cc t cdd t cdz t di t da o 1 data input/ output propagation delay: data transfer: bytewide parallel data bus (8) all inputs all inputs t pd

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